ISSCC: Background calibration boost for ADC

At the International Solid-State Circuits Conference in San Francisco, Analog Devices revealed a 20-bit 1Msample/s successive approximation ADC with 0.3ppm INL (integral non‑linearity). Key to this performance is a constantly-running background calibration technique that allows the ADC to process its input signal without interruption, while compensating for ageing, temperature sensitivity, package stress and PCB stress. ...
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