New technology reduces 30% chip area of STT-MRAM while increasing memory bit yield by 70% - Science Daily

New technology reduces 30% chip area of STT-MRAM while increasing memory bit yield by 70%
Science Daily
Date: May 17, 2016; Source: Tohoku University; Summary: Researchers have successfully developed a technology to stack magnetic tunnel junctions directly on the vertical interconnect access. Share: FULL STORY ...and more »